Semiconductor device with low thermally generated leakage current

ABSTRACT

A semiconductor device in the form of a metal insulator field effect transistor (MISFET) (200) is constructed as a heterostructure of narrow bandgap In 1-x  Al x  Sb semiconductor materials. The MISFET (200) is formed from four semiconducting layers (112 to 118) arranged in series as follows: a heavily doped p-type first layer (112), a heavily doped relatively wider bandgap p-type second layer (114), a lightly doped p-type third layer (116) and a heavily doped n-type fourth layer (118). A source (202) and a drain (204) are formed in the fourth layer (118) and a gate (116/205) in the third layer. An n +  p -  junction (124) is formed between the third and fourth layers and a p +  p -  junction (122) between the second and third layers. The second layer (114) provides a conduction band potential energy barrier to minority carrier (electron) flow to the gate (116/205), and is sufficiently wide to prevent tunnelling of minority carriers therebetween. The first and second layers (112, 114) in combination provide a p +  p +  excluding contact to the third layer (116). The n +  p -  junction (124) between the third and fourth layers (116, 118) is an extracting contact; when reverse biased in operation, this junction (124) extracts minority carriers from the region of the third layer (116) adjacent the collector (118/204). In operation, the third layer (116) incorporating the gate (205) becomes depleted of charge carriers and therefore exhibits greatly reduced leakage current. In consequence, the MISFET (200) has good dynamic range in terms of controllable drain current. The invention also provides bipolar transistors (300, 400 ) and related devices.

BACKGROUND OF THE INVENTION

1. FIELD OF THE INVENTION

This invention relates to a semiconductor device. More particularly,though not exclusively, it relates to such devices which areheterostructures of narrow bandgap semiconductor materials.

2. DISCUSSION OF PRIOR ART

Narrow bandgap semiconductors such as InSb have useful properties suchas very low electron effective mass, very high electron mobility andhigh saturation velocity. These are potentially of great interest forhigh speed device applications. Unfortunately it has proved difficult toovercome the drawbacks of these materials. A prior art three terminalactive device which is a narrow bandgap semiconductor materialheterostructure is described by T Ohashi et al in J Vac Sci Technol B4622 (1986). It is a thin film depletion mode field effect transistor(FET) device, and consists of an InSb film on a GaAs substrate. However,the device of Ohashi et al unfortunately has poor performance, a highleakage current in particular. It has a dynamic range of only 7dB, andso its current in an ON state is only about twice (5^(1/2)) that in anOFF state. This exemplifies the difficulty of exploiting the usefulproperties of narrow bandgap semiconductors.

European Patent Application No.8530405.1-2203 published as No. 0 167 305corresponding to U.S. Pat. No. 5,016,073 discloses photodiodes havingtwo or more terminals and formed as heterostructures of semiconductormaterials. There is no disclosure of field effect transistors or bipolartransistors.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an alternative form ofsemiconductor device.

The present invention provides a semiconductor device having first,second and third semiconducting regions connected in series for currentinput, current control and current output respectively and each arrangedto be biased by a respective biasing means, the device incorporating anextracting contact arranged to extract minority carriers from the secondregion, and the second region being of low doping and having a commoninterface with a fourth semiconducting region itself having a commoninterface with a fifth semiconducting region, and wherein the fourthregion:

(a) has like majority carrier type to that of the fifth region.

(b) is biasable through the fifth region and is arranged to act as anexcluding contact to exclude minority carriers from at least parts ofthe second region adjacent the third region and thereby to reduce theintrinsic contribution to current reaching the third region,

(c) has a bandgap sufficiently large to provide a potential energybarrier to minority carrier flow from the fifth region to the secondregion,

(d) has sufficiently high doping to counteract potential barrierimpediment to majority carrier flow from the second region to the fifthregion, and

(e) is less wide than a critical thickness associated with dislocationformation but sufficiently wide to inhibit tunnelling of minoritycarriers from the fifth region to the second region.

The expressions "extracting contact" and "excluding contact" are knownin the art of semiconductor devices. The former relates to a junctionwhich gathers minority carriers which diffuse to it, and the latter ajunction which accepts majority carriers but does not supply minoritycarriers.

The invention provides the advantage that it makes possible theproduction of devices not produced in the prior art and the attainmentof improved dynamic range: an enhancement mode field effect transistorembodiment of the invention formed from narrow bandgap semiconductormaterial has exhibited a dynamic range of 23dB. Such an FET device hasnot been made in the prior art. Moreover, this embodiment has a dynamicrange which is a 16dB improvement over a prior art depletion mode deviceformed from narrow bandgap semiconductor material. In such embodiment ofthe invention, the first, second and third regions are source, gate anddrain regions respectively, and the first and third regions are of likemajority carrier type opposite to that of the second, fourth and fifthregions.

The invention may alternately be arranged as a depletion mode fieldeffect transistor, in which case the first, second and third regions aresource, gate and drain regions of like majority carrier type opposite tothat of the fourth and fifth regions.

The second region may be a layer having first and second sides separatedby the layer thickness, the first and third regions being connected tothe first side of the second region, the fourth region being connectedto the second side of the second region and the fifth region beingconnected to a side of the fourth region remote from the first, secondand third regions. The fourth region may be connected to the secondregion over an area at least as extensive and correspondingly located asthose parts of the second region adjacent and between the first andthird regions, the fourth region being arranged to provide minoritycarrier exclusion over most or all of the second region.

A device of the invention may have constituent semiconductor materialswith narrow bandgaps, i.e. bandgaps less than 0.5eV.

In a preferred embodiment, the invention is an enhancement mode fieldeffect transistor having the following constituent regions:

(a) first and third regions of InSb having an n-type dopantconcentration of at least 2×10¹⁷ atoms/cm³,

(b) a second region of InSb having a p-type dopant concentration of lessthan 1×10¹⁷ atoms/cm³,

a fourth region of In_(1-x) Al_(x) Sb having a p-type dopantconcentration of at least 5×10¹⁷ atoms/cm³ where x is a compositionalparameter in the range 0.01 to 0.7, and

(d) a fifth region of InSb with a p-type dopant concentration of atleast 5×10¹⁷ atoms/cm³.

The invention may be formed from a series of layers disposedsuccessively on a common substrate, the fifth region being a first layersupported by the substrate, the fourth region being a second layer incontact with the fifth layer, the second region being a third layer incontact with the second layer, and the first and third regions beingformed from a common fourth layer in contact with the third layer.

In an alternative embodiment, the invention is a bipolar transistor inwhich the first, second and third regions are emitter, base andcollector regions respectively, and the first and third regions are oflike majority carrier type opposite to that of the second, fourth andfifth regions. In a preferred version of this embodiment, the secondregion is a layer having first and second sides separated by the layerthickness, the first and third regions are connected respectively to thefirst and second sides of the second region, the fourth region isconnected on one side to the first side of the second region and on theother side to the fifth region. The second region may have a furtherbiasing means connected to a different part of the second region to thatto which the fourth region is connected; this further biasing means maybe biasable independently of the fourth region and may incorporatesemiconducting regions of like composition to those of the fourth andfifth regions. The further biasing means and the fourth region may beannular and disposed around the first region.

A bipolar transistor of the invention may incorporate the following:

(a) first and third regions of InSb having an n-type dopantconcentration of at least 2×10¹⁷ atoms/cm³,

(b) a second region of InSb having a p-type dopant concentration of lessthan l×10¹⁷ atoms/cm³,

(c) a fourth region of In_(1-x) Al_(x) Sb having a p-type dopantconcentration of at least 5×10¹⁷ atoms/cm³, where x is a compositionalparameter in the range 0.01 to 0.7, and

(d) a fifth region of InSb with a p-type dopant concentration of atleast 5×10¹⁷ atoms/cm³.

A device of the invention may incorporate a fourth region ofsemiconductor bandgap at least (3kT/q) Volts, preferably (5kT/q) Volts,wider than that of either the second region or the fifth region, where kis the Boltzmann constant, T the absolute temperature and q theelectronic charge.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the invention might be more fully understood, embodimentsthereof will now be described, by way of example only, with reference tothe accompanying drawings, in which:

FIG. 1 schematically illustrates a semiconductor heterostructure;

FIG. 2 schematically illustrates a semiconductor heterostructure in theform of an extracting diode;

FIG. 3 graphically illustrates variation of conduction band and valenceband edge energies along the FIG. 2 diode;

FIG. 4 graphically illustrates variation of the product of zero biasresistance and area with temperature for diodes respectively with andwithout minority carrier barrier layers;

FIG. 5 graphically illustrates the reverse bias current-voltage anddifferential conductance-voltage characteristics, at 70° C., of an InSbdiode of the invention;

FIG. 6 schematically illustrates a semiconductor heterostructure grownproduce a MISFET of the invention;

FIG. 7(a-d) schematically illustrates stages in the fabrication of aMISFET of the invention from the heterostructure of FIG. 6:

FIG. 8 graphically illustrates output characteristics of a MISFET of theinvention;

FIG. 9 is a schematic cross-sectional view of a bipolar transistor ofthe invention; and

FIG. 10 is a schematic cross-sectional view of a further embodiment of abipolar transistor of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Referring now to FIG. 1, there is shown schematically a semiconductormultilayer heterostructure 10 suitable for constructing devices of theinvention. The heterostructure 10 consists of indium antimonide (InSb)and indium aluminium antimonide (In_(1-x) Al_(x) Sb) alloys. It has fourregions of semiconductor material as follows: a heavily doped narrowbandgap p-type (p⁺) region 12, a relatively wide bandgap heavily dopednarrow bandgap p-type (p⁺) region 14, a lightly doped p-type (p⁻) region16 and a heavily doped narrow bandgap n-type (n⁺) region 18. In thisspecification a superscript minus (-) or plus (+) indicates light orheavy doping respectively, the absence of a superscript indicates anintermediate doping level. The bar (.sub.) subscript indicates materialof wide bandgap relative to the bandgap of material denoted without thebar. Adjacent pairs of the regions 12, 14, 16 and 18 have respectiveintermediate regions indicated by lines 20, 22 and 24, and which p⁺ p⁺,p⁺ p⁻ and p⁻ n⁺ junctions respectively. Regions 20 and 22 areheterojunctions and region 24 is a homojunction, and all three arereferred to as junctions hereinafter.

The heterostructure 10 is grown in a VG V80H MBE system on a p-type(cadmium doped to 3×10¹⁴ cm⁻³) (001) InSb substrate 26. Adjacent to thesubstrate 26 is a buffer and temperature ramp region 28 grown whilst theMBE system was being set up correctly to grow the heterostructure 10.The growth temperature was approximately )420° C. and the growth racewas 0.5 micronshr⁻¹. Mesa diode fabrication is performed using standardphotolithographic techniques, on the heterostructure 10, to definechemically etched structures.

The p⁺, p⁻ and n⁺ regions 12, 16, 18 consist of InSb of widths 2.15microns, 3.15 microns, and 3.O microns respectively. InSb has a bandgapof O.18eV at room temperature. The p⁺ region 14 consists of In₀.9 Al₀.1Sb of width 0.02 microns. In₀.9 Al₀.1 Sb has a bandgap at roomtemperature of 0.36eV, twice the bandgap of InSb. Dopants are silicon(Si) for n-type and beryllium (Be) for p-type. Doping in regions 12 and14 is 5×10¹⁸ atoms cm⁻³, in region 16 is 1×10¹⁵ atoms cm⁻³ and in region18 is 1×10¹⁸ atoms cm⁻³.

Referring now to FIG. 2, there is shown schematically a semiconductordevice 30 in the form of a diode. The diode 30 will be described inorder to clarify the roles of excluding contacts, extracting contactsand potential barriers employed in devices of the invention. Partscommon to FIG. 1 are like referenced. The diode 30 is composed ofregions 12, 14, 16 and 18 with intervening junctions 20, 22 and 24 asdescribed with reference to FIG. 1. As will be described later, the p⁺p⁻ junction 22 forms an excluding contact and the p⁻ n⁺ junction 24forms an extracting contact. Electrodes to the diode 30 are provided at32 and 34 for bias voltage application.

Region 12 provides a narrow bandgap region to which the electrode 32 maybe attached and the width of this region is not critical. In thisembodiment region 12 has width of 2.15 microns between electrode 32 andjunction 22. Region 14 must have sufficient width such that minoritycarriers are substantially prevented from tunnelling from region 12 toregion 16, that is wider than about 2nm. This is discussed in moredetail later. However, region 14 must also be narrower than the criticalwidth for strain relief; this critical width is a term of art for thelayer thickness, which, if exceeded, results in the layer failing toaccommodate strain associated with conformity with the layer's substratecrystal lattice. Layers with widths above the critical width havedislocations giving rise to unwanted energy states which conflict withdevice operation. In In₀.9 Al₀.1 Sb, the critical width is estimated tobe 5Onm (from a model by J W Matthews and A E Blakeslee in J CrystalGrowth 27, 118 (1975), Region 14 has a width between junctions 20 and 22of 20nm, less than half the estimated critical width. Region 16 shouldhave a thickness between junctions 22 and 24 which is not greater than aminority carrier diffusion length, in order that the minority carrierexclusion and extraction effects produced within it by these junctionsextend throughout its thickness, it is also important that there is nosource of minority carriers to region 16, that is no electricalconnections through which minority carriers may be injected into thisregion. If there were such a source, exclusion and extraction effectswould be nullified.

In the diode 30 region 16 has a width between junctions 22 and 24 of3.15 microns. Region 18 provides for carrier extraction; its widthshould be greater than a minority carrier diffusion length, e.g. a widthbetween junction 24 and electrode 34 of 3.0 microns.

Referring now also to FIG. 3, this provides curves 40 and 42illustrating graphically the variation in conduction and valence bandedge energies, E_(c) and E_(v) respectively, along the diode 30, at zerobias. Chain lines 44, 46 and 48 indicate positions of junctions 20, 22and 24 respectively. A dashed line 50 indicates the Fermi level throughthe diode 30. The p⁺ region 14 produces a potential barrier 52 in theconduction band which prevents minority carriers (electrons) from the p⁺region 12 entering the p⁻ region 16. In addition, because the bandgap ofthe p⁺ region 14 is wider than that of other regions, electrongeneration in it by thermal excitation is relatively small. The p⁺ p⁻junction 22 therefore forms an excluding contact which excludeselectrons (minority carriers) from reaching the region 16 from its left.The p⁺ region 14 must, however be sufficiently wide to prevent anysubstantial degree of minority carrier transport from region 12 toregion 16 by quantum mechanical tunnel effect through the potentialbarrier 52.

The width required for the region 14 is a function of the form of thepotential energy barrier 52 and the carrier effective mass. Anapproximate analysis is derived from R. A. Smith, "Wave Mechanics ofCrystalline Solids" 2nd edition, Chapman and Hall (1969) page 56, for arectangular barrier with equal conduction and valence band edgeenergies, E_(c) and E_(v), on either side of the barrier. Moreover theelectric field developed across the barrier 52 should be small so thatthere is little resistance to the majority carrier flow. In the case ofa conduction band barrier to electron flow, the proportion of electrons.P, which will penetrate the barrier is given by: ##EQU1## where E is theelectron energy with E_(c) defined to be zero, N(E) is the density ofstates in the conduction band, F(E) is the Fermi function and t(E) isthe tunnelling probability per electron. The tunnelling probability perelectron is given by: ##EQU2## where W is the barrier height, a is thebarrier width (i.e. the width of region 14) and b is given by:

    b=2π{2m.sup.* (W-E)}.sup.1/2 /h                         (3)

where m^(*) is the electron effective mass and h is Planck's constant.

A consequence of a valence band offset is a discontinuity spike such as54 or 56. This may cause a barrier to majority carrier (hole) flow whichis undesirable. Therefore doping in the p⁺ region 14 is arranged to besufficiently high for tunnelling through the spikes 54, 56 to occur,thus effectively removing the barrier to hole flow. Alternatively somedegree of compositional grading may be employed at the heterojunctions20 and 22 to prevent the formation of discontinuity spikes 54 and 56.This involves a gradual change of the compositional parameter x' inIn_(l-x') Al_(x') Sb from 0 to x' and x' to 0 respectively overdistances of the order of 10nm at these heterojunctions. Suchcompositional change is well known in the art and will not be described.

The diode 30 operates as follows. Electrode 32 is negatively biased withrespect to electrode 34. The p⁻ n⁺ homojunction 24 provides therectifying characteristics of the diode 30, and is reverse biased. Asmentioned previously the p⁺ p⁻ heterojunction 22 provides an excludingcontact, that is holes (majority carriers) flow freely from region 16 toregion 14 but only a small electron (minority carrier) current may flowin the reverse direction from region 14 to region 16. In additionjunction 24 provides an extracting contact, because electrons diffusefrom region 16 to region 18 as a result of the lower conduction bandedge energy in region 18. In consequence, electrons in region 16 whichdiffuse to the reverse biased p⁻ n⁺ junction 24 are extracted to theregion 18, and cannot be replenished from the region 14 because of theexcluding contact properties of junction 22. The electron (minoritycarrier) concentration in region 16 consequently falls when the diode 30is reverse biased, and charge neutrality considerations dictate that thehole (majority carrier) concentration fall with it. The combination ofthese two effects is to reduce the intrinsic contribution to conductionin the region 16 when the diode 30 is reverse biased. The intrinsiccontribution is that arising from excitation of valence electrons, asopposed to the extrinsic contribution arising from excitation ofimpurity states. In the absence of bias, the region 16 is intrinsic atthe diode operating temperature, i.e. conductivity is predominantly thatdue to thermal ionisation of valence electrons. Under bias, a dynamicsituation arises in which carrier concentrations fall sufficiently suchthat the region 16 behaves extrinsically at the operating temperature.i.e. conductivity becomes predominantly that due to thermal ionisationof impurity states.

The existence of negative differential resistance in the reverse biascurrent-voltage characteristics of devices of the type described in theprior art has been described by, for example, A. M. White in InfraredPhysics, Vol 27, No 6, (1987) page 361. This negative differentialresistance arises from the suppression of Auger generation mechanisms inthe intrinsic region 16 of the diode 30 as free carriers are removed bythe application of a reverse bias, leading to a reduction in the diodeleakage current. The effect is significantly stronger in devices of theinvention, and provides the advantage of reduced leakage current andimproved performance.

Devices of the invention based on the general form of theheterostructure 10 may have regions equivalent to regions 12, 14, 16 and18 but of different widths. The criteria for region widths discussedabove indicate that these widths should fall within the followingranges. Region 12 may have a width greater than 0.1 microns, region 14 awidth in the range 2nm up to the critical thickness associated withstrain relief , region 16 a width less than or of the order of 3 micronsand region 18 a width greater than 0.1 microns.

Doping levels and the dopants used may also vary with the exactrequirements for device operation. Doping in p⁺ region 12 should besufficiently high that conductivity is extrinsic, i.e. it should bepredominantly due to majority carrier (hole) transport at thetemperature of operation; High doping in region 12 minimises the seriesresistance presented by this region. A value of at least 5×10¹⁷ atomscm⁻³, preferably at least l×10¹⁸ atoms cm⁻³ is appropriate. Doping in p⁺region 14 is preferably sufficiently high to allow tunnelling ofmajority carriers through valence band discontinuity spikes at junctions20 and 22. The acceptor concentration N_(a) in region 14 should be atleast 5×10¹⁷ atoms cm⁻³, preferably at least 1×10¹⁸ atoms cm⁻³. Dopingin p⁻ region 16 should be sufficiently low to produce predominantlyintrinsic characteristics at the diode operating temperature at zerobias, that is N_(A) not greater than l×10¹⁷ atoms cm⁻³ for ambienttemperature operation. Doping in n⁺ region 18 should be sufficientlyhigh to produce strong degeneracy and minimise hole injection in p⁻region 16; Region 18 should therefore have a donor concentration N_(D)of at least 2×10¹⁷ atoms cm⁻³ , preferably l×10¹⁸ atoms cm⁻³. The dopinglevels given above are electrically active levels. Regions 12 and 14will always be of like majority carrier type opposite to that of region18. However region 16 may be p-type or n-type. The rectifying junctionmay therefore be junction 22 or 24. If junction 22 were to berectifying, junction 24 would function as the excluding contact.

In an InSb/In_(1-x) Al_(x) Sb heterostructure used to provide devices ofthe invention, the material of region 16 may have a value of theparameter x in the range 0.01 to 0.7, preferably 0.1 to 0.3. However theinvention is not limited to InSb/InAlSb heterostructures but may beconstructed from a variety of different semiconductor materials.

A figure of merit for diodes is the zero bias resistance R₀ multipliedby the diode junction area A, hence R₀ A. Referring now to FIG. 4, thevariation of R₀ A with the inverse of the temperature (x1000) isillustrated graphically for an InSb diode 30 and for two diodes withoutbarriers equivalent to 52. Data points plotted with a square symbolcorrespond to the diode 30, and the like for the two other diodes arerepresented by crosses and circles respectively. The higher the value ofR₀ A the better the performance of a diode. From FIG. 4 it can be seenthat the diode 30 is significantly better than the other two for alltemperatures above 13OK.

Referring now to FIG. 5, reverse bias current-voltage and differentialconductance-voltage characteristics are illustrated graphically bycurves 70 and 72 respectively, for a diode operating at 70° C. The axisfor current is shown on the right of FIG. 5 with units of mA. The axisfor conductance is shown on the left of FIG. 5 with units of mS. Thediode used to obtain the results of FIG. 5 will be referred to as 30',since it was as described above for diode 30, with the exception thatregion 14 comprised material with composition In₀.8 Al₀.2 Sb. Curve 72illustrates a negative conductance between points 74 and 76. Thus thediode 30'illustrated negative differential resistance, of the kinddescribed above.

Referring now to FIG. 6, a semiconductor heterostructure 100 as grown toproduce a MISFET of the invention is illustrated schematically. HereMISFET is an acronym of Metal-Insulator-Semiconductor Field EffectTransistor. The heterostructure 100 is similar to the heterostructure 10used to construct the diode 30, and is grown similarly to theheterostructure 10. Parts common to FIGS. 1 and 2 are similarlyreferenced but with the addition of a prefix 100. The p⁺, p⁺, p⁻ and n⁺regions 112, 114, 116 and 118 respectively are arranged in upwardsuccession as described in relation to regions 12 to 18 in theheterostructure 10. The p⁺ region 112 is adjacent to a ramp region 128.Regions 112, 116 and 118 are formed of appropriately doped InSb ofwidths 2.0 microns, 0.25 microns and 0.75 microns respectively. Region114 is formed of appropriately doped In⁰.9 Al₀.1 Sb of width 2Onm. Thedopant in p-type regions 112 and 114 is beryllium and in the n-typeregion 118 is silicon. Doping levels are 3×10¹⁸ atoms cm⁻³ in regions112 and 114, 1×10¹⁵ atoms cm⁻³ in region 116 and 2×10¹⁸ atoms cm⁻³ inregion 118. These doping levels are estimated electrically activelevels, the chemical level of dopant will be slightly higher in eachcase. Doping in the p⁻ region 116 is generally achieved due to machineimpurity background. However, the doping may also be achievedconventionally as for the other regions 112, 114 and 118 if a higherdoping level is desired. It is convenient but not essential for regions112 and 114 to have like doping levels.

Referring now also to FIG. 7, steps in the process of fabricating aMISFET 200 from the heterostructure 100 shown in FIG. 6 areschematically illustrated in drawing parts 7(a) to 7(d). Parts describedearlier are like referenced. The MISFET fabrication is performed on theInSb substrate 126 using a mask set which gives several hundredtransistors 200 in an array. The heterostructure 100 grown as describedabove is cleaved into 6 mm by 6 mm square chips. A chip is then etchedto form a number of transistors each within a respective area 100microns square. Each chip also has a region free of transistors uponwhich terminals and common connections are formed. As shown in FIG.7(a), etching of the chip produces source and drain mesas, 202 and 204respectively, for each transistor 200. A gate depression 205 is thenformed between the source and drain mesas 202 and 204. The depression205 has a depth of 1.0 microns, a length of 20 microns and a widthperpendicular to the plane of FIG. 7 of 40 microns. A further etchingstage is then performed to define the limits of each transistor 200, asshown in FIG. 7(b). This involves etching down into the p⁺ region 112 toleave source and drain mesas 202, 204 as part of a remaining upstandingportion 206 incorporating regions 114 to 118 and part of region 112.This etching also leaves an exposed surface 208 of the p⁺ semiconductorregion 112. The upstanding portion 206 and the surface region 208 areanodized, then silicon oxide (SiO.sub. x) is sputtered on andpreferentially etched to form a gate insulator 210 and source and draincontact insulators 212 and 214 respectively, as shown in FIG. 7(c). Anarea 221 of the surface region 208 is masked (not shown) duringsputtering to keep it free of silicon oxide. As shown in FIG. 7(d), thefollowing metal contacts are subsequently deposited: gate 216, source218, drain 220 and common 222.

Carrier extraction and exclusion take place in the MISFET when biasedfor normal operation. As in the case of the diode 30, the n⁺ p⁻ junction124 in the drain mesa 204 acts as an extracting contact removingelectrons (minority carriers) from the region 116. Such electrons cannotbe replenished from the region 114, because it acts in combination withthe region 112 as an excluding contact and a potential barrier toelectrons. The electron concentration in region 116 therefore falls whenthe MISFET 200 is biased, and with it the hole concentration in thatregion. This greatly reduces the conductivity in the region 116, whichtherefore reduces the leakage current between the source 202 and drain204.

As illustrated in FIG. 7, the excluding contact regions 112/114 extendacross the full width of the MISFET 200. This is not in fact essentialin an enhancement mode MISFET: this device is required to have carrierexclusion in the region 116 in the immediate vicinity of the n⁺ p⁻junction 124 in the drain mesa 204, but not necessarily elsewhere in theregion 116. This is not however the case for embodiments to be describedlater.

Referring now also to FIG. 8, output characteristics at room temperatureof the MISFET 200 are illustrated graphically. FIG. 8 shows curves 250to 266 of the variation of drain current I_(D) with drain-source voltageV_(DS) for nine different values of gate voltage V_(G) ; V_(G) ismeasured relative to the source contact. Curve 250 corresponds to V_(G)of 1.5V and curve 266 to V_(G) of 5.5V. The curves 252 to 264 correspondto values of V_(G) intermediate these two values and increasing in stepsof 0.5V; i.e. curve 250+2N corresponds to V_(G=) 1.5+0.5N, where N=0 to8. The output characteristics are generally of the classical form forMISFETs, which is evidence that a viable MISFET has been produced. At atypical operating drain-source voltage V_(DS) of 350mV indicated byarrows 270, the drain current is switchable from 2.5mA (curve 266) tojust under 0.16mA (curve 250) by changing the gate voltage V_(G) from5.5V to 1.5V. These output characteristics correspond to a dynamic rangeof 23dB and a maximum transconductance (g_(m)) of 25 milli-Siemens pepmm (mSmm⁻¹). It is believed that this is the first known example of anenhancement mode MISFET made of narrow band semiconductor materials(E_(g) < 0.7eV). A prior art depletion mode device is known having adynamic range of only 7dB, as previously mentioned.

Parameters such as region widths, doping levels and material compositionx may be varied to optimise device characteristics for particular uses.For a MISFET region widths may be within the following ranges; p⁺ region112 greater than 0.1 microns, p⁺ region 114 from 2nm to the criticalthickness for strain relief, p⁻ region 116 greater than 0.1 microns, n⁺region 118 greater than 0.1 microns. The critical thickness varies withgrowth conditions, but is in the region of 50nm for an InSb/In_(1-x)Al_(x) Sb heterostructure.

The MISFET 200 is an InSb/In_(1-x) Al_(x) Sb heterostructure. There area number of other semiconductor material combinations that are suitablefor construction of devices of to the invention. The criteria forselecting such material combinations will now be described. First andsecond narrow bandgap semiconductor materials are required. The secondmaterial requires a bandgap which is wider than that of the first. Thetwo semiconductor materials need not be lattice matched. The widerbandgap second material should produce an energy barrier in the minoritycarrier band which reduces leakage currents by a factor which dependsexponentially on the potential step V in the minority carrier band andhyperbolically on the barrier width and minority carrier diffusionlength. The reduction in leakage current required will depend on theapplication of the particular device in question. However, for example,to obtain a 10% reduction in leakage current in the InAlSb MISFET device200, V_(ps), should be approximately kT/q; here q is the electroniccharge, k is Boltzmann's constant and T is the operating temperature. Toobtain at least a 50% reduction in leakage current, V^(ps) should be atleast 3kT/q; values of V_(ps), of 5kT/q and 8kT/q correspondapproximately to reductions in leakage current of 90% and 99%respectively.

Combinations of materials that may comply with the above V_(ps) criteriawith suitably chosen composition parameters x, or x and y, includeIn_(1-y) Al_(y) Sb/In_(1-x) Al_(x) Sb, PbSe/PbS, InAs/InAs_(1-x) P_(x),InAs_(1-x) Sb_(x) /In_(1-y) Al_(y) Sb, InAs_(1-x) Sb_(x) /InAs_(1-y)P_(y), GaAs/Ga_(1-x) Al_(x) As, In_(1-x) Ga_(x) Sb/In_(1-y) Al_(y) Sband Hg_(1-x) Cd_(x) Te/Hg_(1-y) Cd_(y) Te. InSb/InAlSb, from theembodiments described above are constructed, is a special case of thefirst of these with the parameter y equal to zero.

For semiconductor systems in which the / relatively narrow bandgapmaterial has a bandgap significantly less than that in silicon orgallium arsenide, i.e. a bandgap E_(g) of less than or about 0.5eV,there are advantages due to the speed of carrier flow. Low bandgapmaterials are often characterised by high carrier mobility. They havebeen ignored for conventional signal processing systems because thermalexcitation of carriers in them is unacceptable at room temperature. Thepresent invention provides the potential for devices to be constructedto operate at speeds faster than is possible in either silicon orgallium arsenide. For instance the maximum speed of carrier flow in InSbis of the order of a factor of five faster than in silicon. There arealso advantages relating to the power dissipation in the narrow bandgapmaterials. For example, in a bipolar transistor the power-delay product(Pt) figure of merit is, fundamentally, determined by the energydissipated in charging and discharging the emitter-base junctioncapacitance. CV² /2, where C is the capacitance and V the voltage whichit is charged. Both parameters C and V can be substantially reduced inthe narrow bandgap materials.

The current I which can flow through a forward biased emitter-basejunction is given by:

    I=I.sub.0 (e.sup.qV/kT -1)                                 (4)

The value of I₀ can vary by many orders of magnitude from onesemiconductor to another. However, the most significant term in I₀ isthe square n₁ ² of the intrinsic carrier concentration n_(i) ; i.e.

    I is approximately proportional to n.sub.i.sup.2 (e.sup.qV/kT -1)(5)

For large forward bias, this gives:

    I is approximately proportional to e.sup.-Eg/kT e.sup.qV/kT =e.sup.(q/kT)(V-Eg/q)                                     (6)

To obtain a given current, therefore, the applied voltage should beapproximately (E_(g) /q)+C, where C is only a weak function of the typeof semiconductor. In order to achieve the maximum current from thetransistor, the emitter-base junction is biased to a virtually flat-bandcondition, i.e. V_(max) is approximately E_(g) /q. Hence I_(max) tendsto a constant for all semiconductors, independent of bandgap, and thenecessary applied voltage is approximately equal to the bandgap, e.g.V_(InSb) is approximately V_(si) /5. Thus the power in a switchingcircuit may be reduced by a factor of up to 25.

In a logic circuit the time for the transistor to switch between statesis fundamentally determined by the carrier transit time from the neutralregion of the emitter to the neutral region of the collector. In thelimit, this is equal to d_(dep/V) _(s), where d_(dep) is the distance tocontain the emitter-base and base-collector depletion regions, and v_(s)is the saturated carrier velocity. The capacitance C of each depletionregion is inversely proportional to its width; hence, for a givenswitching time, C is approximately proportional to 1/v_(s). Moreover,for example, C_(InSb) is approximately equal to C_(si) /5, whereC_(Insb) and C_(si) are the values of C in InSb and Si respectively.Hence the power P is also reduced by an additional factor of 5.

The invention is not limited to the devices described thus far. Inaddition to MISFETs other forms of transistor may also be constructed,for example junction FETs, depletion mode FETs, enhancement mode FETsand hereto junction bipolar transistors. More generally theheterostructure described may be employed in any heterostructure devicewhere difficulties exist in forming contacts to a wide bandgap p-typematerial.

Referring now to FIG. 9, there is shown a further embodiment of theinvention in the form of a bipolar transistor indicated generally by300. The transistor 300 is of generally disc-shaped construction, and isillustrated in section through a diameter and through the disc symmetryaxis indicated by chain lines 302. It has an n⁺ emitter 304, a p⁻ base306 and an n⁺ collector 308. An excluding contact 310 of annular shapeis connected to the base 306, the contact incorporating a p⁺ lower layer312 and a p⁺ upper layer 314. The transistor 300 has electrical biaselectrodes 316, 318 and 320 for the emitter 304, base 306 and collector308 respectively.

The transistor 300 is formed of InSb and In₀.9 Al₀.1 Sb with dopantspecies and concentrations as previously described; i.e. regions 304,306, 308, 312 and 314 have compositions like to those of regions 118.116, 118 (once more), 114 and 112 respectively in the heterostructure100 of FIG. 6.

The operation of the transistor 300 is as follows. Bias voltages areapplied to the electrodes 316, 318 and 320 to achieve transistoroperation with base current drawn through the base electrode 318.Minority carriers are extracted from the base 306 by the n⁺ p⁻interfaces between the emitter 316 and base 306 and collector 308 andbase 306, which are extracting contacts. These carriers cannot bereplenished from the p⁺ p⁺ excuding contact formed by layers 312 and314. The minority carrier concentration therefore falls in the base 306,and with it that of majority carriers from charge neutralityconsiderations. This reduces the base conductivity. Conduction throughthe base 306 between the emitter 304 and collector 308 is therefore afunction of the base bias current in addition to the bias voltages onthe emitter/base and base/collector junctions. This makes it possible toachieve relatively high dynamic range in the ratio of collector currentsbetween transistor "ON" and "OFF" states. The transistor 300 istherefore suitable for digital switching applications.

Unlike the MISFET 200, it is important that carrier extraction andexclusion take place over substantially all of the base 306 in order toachieve good transistor performance, this is because a non-extractedregion extending between emitter and collector acts as a short circuit.

Referring now also to FIG. 10, a further bipolar transistor embodimentof the invention is shown and is indicated generally by 400. It issimilar to the transistor 300, and like features are like referencedwith a prefix 400 substituted for 300. The following description will bedirected to aspects of difference. As compared to the transistor 300,the transistor 400 has an additional annular base contact assemblyindicated by suffix "a" to its elements; these elements are an excludingcontact 410a, its lower and upper layers 412a and 414a, and a base biasterminal 418a.

The additional base contact 410a is an A.C. signal input, and isinterposed between a D.C. bias current base contact 410 and an emitter404. The transistor 400 is D.C. biased as described for the previousembodiment 300 using bias electrodes 416, 418 and 420. An A.C. signal isthen applied to the signal base electrode 418a, and this signal producesmodulation of the transistor current with consequent amplification. Thetransistor 400 has the advantage that electrical noise associated withthe comparatively large base bias current does not appear on the muchsmaller A.C. input signal. This embodiment therefore appropriate forsmall signal analogue amplification.

We claim:
 1. A semiconductor device having first, second and thirdsemiconducting region connected in series for current input, currentcontrol and current output respectively and each arranged to be biasedby a respective biasing means, wherein the device includes an extractingcontact comprising a means for extracting minority carriers from thesecond region and the second region is of low doping and has a commoninterface with a fourth semiconducting region, said fourthsemiconducting region having a common interface with a fifthsemiconducting region, and wherein the fourth region:(a) has likemajority carrier type to that of the fifth region, (b) is biasablethrough the fifth region and comprises an excluding contact means forexcluding minority carriers from at least parts of the second regionadjacent the third region and thereby to reduce the intrinsiccontribution to current reaching the third region, (c) has a bandgapsufficiently large to provide a potential energy barrier to minoritycarrier flow from the fifth region to the second region, (d) hassufficiently high doping to counteract potential barrier impediment tomajority carrier flow from the second region to the fifth region, and(e) is less wide than a critical thickness associated with dislocationformation but sufficiently wide to inhibit tunnelling of minoritycarriers from the fifth region to the second region.
 2. A deviceaccording to claim 1 wherein it is a field effect transistor in whichthe first, second and third regions are source, gate and drain regionsrespectively, and the first and third regions are of like majoritycarrier type opposite to that of the fourth and fifth regions.
 3. Adevice according to claim 2 wherein it is an enhancement mode fieldeffect transistor in which the second region is of like majority carriertype to that of the fourth and fifth regions.
 4. A device according toclaim 3 wherein the second region is a layer having first and secondsides separated by the layer thickness, the first and third regions areconnected to the first side of the second region, the fourth region isconnected to the second side of the second region and the fifth regionis connected to a side of the fourth region remote from the first,second and third regions.
 5. A device according to claim 4 wherein thefourth region is connected to the second region over an area at least asextensive and correspondingly located as those parts of the secondregion adjacent and between the first and third regions, the fourthregion being arranged to provide minority carrier exclusion over most orall of the second region.
 6. A semiconductor device having first, secondand third semiconducting regions connected in series for current input,current control and current output respectively and each arranged to bebiased by a respective biasing means, wherein the device includes anextracting contact comprising a means for extracting minority carriersfrom the second region, and the second region is of low doping and has acommon interface with a fourth semiconducting region, said fourthsemiconducting region having a common interface with a fifthsemiconducting region, and wherein the fourth region:(a) has likemajority carrier type to that of the fifth region, (b) is biasablethrough the fifth region and comprises an excluding contact means forexcluding minority carriers from at least parts of the second regionadjacent the third region and thereby to reduce the intrinsiccontribution to current reaching the third region, (c) has a bandgapsufficiently large to provide a potential energy barrier to minoritycarrier flow from the fifth region to the second region, (d) hassufficiently high doping to counteract potential barrier impediment tomajority carrier flow from the second region to the fifth region, and(e) is less wide than a critical thickness associated with dislocationformation but sufficiently wide to inhibit tunnelling of minoritycarriers from the fifth region to the second region wherein the fourthregion bandgap is at least 3 kT/q Volts wider than at least one of saidsecond region and said fifth region, where q is the electronic charge, kis Boltzmann's constant and T is the device operating temperature.
 7. Asemiconductor device having first, second and third semiconductingregions connected in series for current input, current control andcurrent output respectively and each arranged to be biased by arespective biasing means, wherein the device includes an extractingcontact comprising a means for extracting minority carriers from thesecond region, and the second region is of low doping and has a commoninterface with a fourth semiconducting region, said fourthsemiconducting region having a common interface with a fifthsemiconducting region, and wherein the fourth region:(a) has likemajority carrier type to that of the fifth region, (b) is biasablethrough the fifth region and comprises an excluding contact means forexcluding minority carriers from at least parts of the second regionadjacent the third region and thereby to reduce the intrinsiccontribution to current reaching the third region, (c) has a bandgapsufficiently large to provide a potential energy barrier to minoritycarrier flow from the fifth region to the second region, (d) hassufficiently high doping to counteract potential barrier impediment tomajority carrier flow from the second region to the fifth region, and(e) is less wide than a critical thickness associated with dislocationformation but sufficiently wide to inhibit tunnelling of minoritycarriers from the fifth region to the second region wherein:(a) thefirst and third regions are of InSb having an n-type dopantconcentration of at least 2×10¹⁷ atoms/cm³, (b) the second region is ofInSb having a p-type dopant concentration of less than 1×10¹⁷ atoms/cm³,(c) the fourth region is of In_(1-x) Al_(x) Sb having a p-type dopantconcentration of at least 5×10¹⁷ atoms/cm³, where x is a compositionalparameter in the range 0.01 to 0.7, and (d) the fifth region is of InSbwith a p-type dopant concentration of at least 5×10¹⁷ atoms/cm³.
 8. Adevice according to claim 7 wherein the fourth region bandgap is atleast 5 kT/q Volts wider than at least one of said second region andsaid fifth region, where q is the electronic charge, k is Boltzmann'sconstant and T is the device operating temperature.
 9. A deviceaccording to claim 1 wherein it is formed from a series of layersdisposed successively on a common substrate, the fifth region being afirst layer supported by the substrate, the fourth region being a secondlayer in contact with the fifth layer, the second region being a thirdlayer in contact with the second layer, and the first and third regionsbeing formed from a common fourth layer in contact with the third layer.10. A device according to claim 1 wherein said device is a bipolartransistor in which the first, second and third regions are emitter,base and collector regions respectively, the first and third regions areof like majority carrier type opposite to that of the second, fourth andfifth regions, and the fourth region comprises a means for providingminority carrier exclusion effects over substantially all of the secondregion.
 11. A semiconductor device having first, second and thirdsemiconducting regions connected in series for current input, currentcontrol and current output respectively and each arranged to be biasedby a respective biasing means, wherein the device includes an extractingcontact comprising a means for extracting minority carriers from thesecond region, and the second region is of low doping and has a commoninterface with a fourth semiconducting region, said fourthsemiconducting region having a common interface with a fifthsemiconducting region, and wherein the fourth region:(a) has likemajority carrier type to that of the fifth region, (b) is biasablethrough the fifth region and comprises an excluding contact means forexcluding minority carriers from at least parts of the second regionadjacent the third region and thereby to reduce the intrinsiccontribution to current reaching the third region, (c) has a bandgapsufficiently large to provide a potential energy barrier to minoritycarrier flow from the fifth region to the second region, (d) hassufficiently high doping to counteract potential barrier impediment tomajority carrier flow from the second region to the fifth region, and(e) is less wide than a critical thickness associated with dislocationformation but sufficiently wide to inhibit tunnelling of minoritycarriers from the fifth region to the second region; wherein said deviceis a bipolar transistor in which the first, second and third regions areemitter, base and collector regions respectively, the first and thirdregions are of like majority carrier type opposite to that of thesecond, fourth and fifth regions, and the fourth region is arranged toprovide minority carrier exclusion effects over substantially all of thesecond region wherein the second region is a layer having first andsecond sides separated by its layer thickness, the first and thirdregions are connected respectively to the first and second sides of thesecond region, and the fourth region is connected on one side to thefirst side of the second region and on the other side to the fifthregion.
 12. A device according to claim 11 wherein the second region isassociated with a further biasing means connected to a different part ofthe second region to that to which the fourth region is connected, andthe further biasing means incorporates semiconducting regions of likecomposition to those of the fourth and fifth regions.
 13. A deviceaccording to claim 12 wherein the further biasing means and the fourthregion are annular and are both disposed about the first region.
 14. Adevice according to claim 10 wherein the fourth region bandgap is atleast 3 kT/q Volts wider than at least one of said second region andsaid fifth region, where q is the electronic charge, k is Boltzmann'sconstant and T is the device operating temperature.
 15. A deviceaccording to claim 10 wherein:(a) the first region and the third regionare of InSb having an n-type dopant concentration of at least 2×10¹⁷atoms/cm³, (b) the second region is of InSb having a p-type dopantconcentration of less than l×10¹⁷ atoms/cm³, and (c) the fourth regionis of In_(1-x) Al_(x) Sb having a p-type dopant concentration of atleast 5×10¹⁷ atoms/cm³, where x is a compositional parameter in therange 0.01 to 0.7, and (d) the fifth region is of InSb with a p-typedopant concentration of at least 5×10¹⁷ atoms/cm³.
 16. A deviceaccording to claim 15 wherein the fourth region bandgap is at least 5kT/q Volts wider than at least one of said second region and said fifthregion, where q is the electronic charge, k is Boltzmann's constant andT is the device operating temperature.
 17. A semiconductor devicecomprising a field effect transistor having semiconducting source, gateand drain regions, and wherein the device includes an extracting contactcomprising a means for extracting minority carriers from the gateregion, the gate region is of low doping and has a common interface witha fourth semiconducting region, said fourth semiconducting region havinga common interface with a fifth semiconducting region, the source anddrain regions have like majority carrier type opposite to that of thegate region and the fourth and fifth regions, the source, gate and drainregions and the fourth and fifth regions each being of semiconductorbandgap less than 0.7 eV, and the fourth region:(a) has like majoritycarrier type to that of the fifth region, (b) is biasable through thefifth region and comprises an excluding contact means for excludingminority carriers from at least parts of the gate region adjacent thedrain region and thereby to reduce the intrinsic contribution to currentreaching the drain region, (c) has a bandgap sufficiently large toprovide a potential energy barrier to minority carrier flow from thefifth region to the gate region, (d) has sufficiently high doping tocounteract potential barrier impediment to majority carrier flow fromthe gate region to the fifth region, and (e) is less wide than acritical thickness associated with dislocation formation butsufficiently wide to inhibit tunnelling of minority carriers from thefifth region to the gate region.
 18. A semiconductor device comprising afield effect transistor having source, gate and drain regions andincorporating an extracting contact comprising a means for extractingminority carriers from the gate region, and wherein the gate region is alayer of low doping interfaced on one side with the source and drainregions and on another side with a fourth semiconducting region, saidfourth semiconducting region interfaced with a fifth semiconductingregion separated from the gate region by the fourth region thickness,the source and drain regions are of like majority carrier type, and thefourth region:(a) has like majority carrier type to that of the fifthregion and opposite to that of the source and drain regions, (b) isbiasable through the fifth region and comprises an excluding contactmeans for excluding minority carriers from at least parts of the gateregion adjacent the drain region and thereby to reduce the intrinsiccontribution to current reaching the drain region, (c) has a bandgapsufficiently large to provide a potential energy barrier to minoritycarrier flow from the fifth region to the gate region, (d) hassufficiently high doping to counteract potential barrier impediment tomajority carrier flow from the gate region to the fifth region, and (e)is less wide than a critical thickness associated with dislocationformation but sufficiently wide to inhibit tunnelling of minoritycarriers from the fifth region to the gate region.
 19. A deviceaccording to claim 18 wherein the fourth region is connected to the gateregion over an area at least as extensive and correspondingly located asthose parts of the gate region adjacent and between the source and drainregions, the fourth region comprising a means for providing minoritycarrier exclusion over most of the gate region.